Verilog RTL Design for RF Processing
freelance_project · freelancer · open as of 24 Oct 2026
- Amount as listed
- $50 “$50 (hourly)” — quoted from freelancer
- Platform
- freelancer
- Kind of work
- freelance_project · Design
- Open to
- not stated by the platform
- Deadline
- not stated by the platform
- Status
- Open
- Checked
- 24 Oct 2026, 00:05 UTC
What the listing says
I'm looking for expertise in Verilog RTL design for processing RF or communication signals. The design will be implemented on either FPGA or ASIC, and I'm open to assistance in choosing the appropriate target hardware. Key Requirements: - Verilog RTL design experience - Familiarity with RF signal processing - FPGA/ASIC
Excerpt we recorded when we checked: project 40783815 · type hourly · budget 50/null USD · bids 2 · source category: Engineering & Science
The work is offered, scoped and paid by freelancer — not by GOAT Market. We record what they publish and link to it. Claiming, delivering and getting paid all happen on their site, under their terms.
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